The prior art for fabrication of microelectronics is dominated by the utility of fabrication facilities that process semiconductor base wafer material which is shaped in a thin and nearly circular wafer format. This format provides for an economy of scale in amortizing the fixed costs for fabrication of each wafer over the plurality of microelectronic circuits, each of which are identically patterned in many places on each wafer. Following the wafer fabrication process, each of the patterned circuits are electronically tested on the wafer using wafer probe test equipment which serves to identify which of these individual patterned circuits functions in a useful manner. Those patterned circuits which are not electronically functioning or useful are typically marked with a small but visible ink dot. The wafer is then diced or sawed so as to separate each of the patterned circuits, after which those ink dots are used to identify which of the individual circuit die are non-functional and require removal from further microelectronic manufacturing steps. Those individual circuit die with no ink dot are therefore known to be good through wafer fabrication, and are further processed into component packaging and ultimately into electronic equipment and systems in common use today.
This method for microelectronic wafer fabrication is typically employed because wafer fabrication is characterized by a random statistical rate of occurrence of defects in the physical or electrical formation of microelectronic structures on the wafer. Typical causes for defects are particle contamination of the wafer surface as it proceeds through each processing step, contamination of the photolithography equipment and tooling used to pattern each wafer, and physical stresses induced on each wafer as a function of the particular fabrication technology employed.
Conventional electronic design practice does not provide for electronic circuits which can function after they have been electronically modified by physical defects that occur in wafer fabrication. In addition, it is not possible to entirely eliminate all of these sources of wafer defects while in the wafer fabrication phase or to know where these defects are located on the wafer prior to an electrical test of the wafer. Therefore, the microelectronic manufacturer has used in the prior art one of four methods for further testing and processing of wafers after their fabrication:
(1) Wafer Probe: In this procedure, an electrical test is performed of each patterned circuit on the wafer prior to dicing or sawing. This is done by using wafer probe equipment which is typically automated to make electrically conductive probe contacts of the test system onto conductive patterns in each circuit, followed by the test system performing a variety of electrical tests which are then interpreted as to whether or not the circuit pattern under test is functional. Should the circuit under test fail an electrical test criteria, the test equipment then places a small ink dot on top of the circuit under test. After the wafer probe tests are completed, some portion of the patterned circuits (typically between 10 and 90 percent) are known to be electrically defective due to the random statistical occurrence of fabrication defects. These circuits are then removed from further processing once the wafer is diced or sawed. This is the most common practice, as the cost of performing this wafer probe electrical testing (to identify and remove defective circuits from further processing at this point) is typically less than the costs which result from performing the remaining manufacturing steps on the defective circuits as well. Regarding the present-day component industry, a cost savings is typically realized when wafer probe testing identifies greater than 10 percent of the circuits as defective, the yield through the remainder of the manufacturing steps is typically greater than 90 percent, and the costs for producing each monolithic circuit and the remaining manufacturing steps (e.g., assembly and testing of the circuit in microelectronic packaging) are comparable.
(2) No Wafer Probe: In cases where the patterned circuits are much smaller in their physical area when compared to the average density for the formation of defects from wafer fabrication, then the statistical yield will typically become higher than the yield associated with the immediate manufacturing steps following wafer fabrication. These immediate manufacturing steps are typically the microelectronic packaging of each circuit die, followed by an electrical test of the completed component to remove the non-functional circuits. An example of this case is the fabrication of simple, single transistors as each pattern on the wafer, where the statistical yield is typically on the order of 90 percent. In this case, it is less expensive not to perform a wafer probe test and then to discard the 10 percent additional microelectronic packages which could have otherwise been saved in method (1) above, after a final component test is performed.
(3) Redundant Programming: In cases where the patterned circuits are very large in their physical area compared to the density of defects occurring from wafer fabrication, the statistical electrical test yield becomes low (under 10%). Regardless of the methods for wafer probe and final manufacturing involving these circuits, the amortized costs for manufacturing these large monolithic circuits increases nearly exponentially as a function of increasing circuit pattern (or die) size. Some manufacturers have elected to incorporate wafer probe schemes in which the individual circuits are patterned to include redundant regions which are then identified by the test system as being electrically functional or non-functional. The test system then determines if the nature of the non-functional circuits permits the re-configuration of the redundant regions to return the circuit under test to complete functionality. If this is possible, then the test system, while still in probe contact with the circuit under test on the wafer, then "programs" the useful circuits to function in the presence of the defective locations. This programming, for example, may involve the electrical "blowing" of a microelectronic resistive fuse-link film, made as part of the circuit under test, which acts to re-configure each circuit to operate properly following this operation. This scheme is typically employed to manufacture high-capacity (256K bits and larger) static random access memory components.
(4) Custom Wafer Patterning: Similar to the redundant programming scheme of paragraph (3) above, a few manufacturers perform all but the final wafer fabrication steps where the last interconnect films are not patterned. In these cases, some of the interconnect films are completed so as to enable wafer probe of the redundant sections of a very large circuit. The wafer probe test system determines which sections are functional and records this information for that wafer in an information data base. This data base becomes a record of where the electrical defects are located on each wafer. This data base is then processed by a computer to output a new data file which is used by an electron-beam photo lithography system for the purpose of custom patterning of each wafer with final layer(s) of interconnect film to complete wafer fabrication. Given that the statistical yield through the wafer fabrication of the final interconnect layer(s) is high, then each circuit is functional with high yield as well. This method is employed for very large circuits requiring a variety of different functions, and for which the high cost for custom patterning of each wafer can be justified.
(5) In-Circuit Testing: Some manufacturers of very large scale integrated (VLSI) components such as microprocessors and gate arrays have employed small test circuits, integrated as part of these larger and more complex circuits which perform in-circuit testing of the circuit. This method is employed as a result of a trend in higher complexities in integrated circuit fabrication which result in circuits which cannot be fully tested by an external test system, made to be brought into probe contact with the die or with the available electrical conductive pins of the package containing the circuit die. This result follows from the inability of an external test system to have adequate coverage of all of the possible electrical states of these complex VLSI circuits, given the number of external connections available with the VLSI circuit. Therefore, these manufacturers include in these VLSI circuits a test circuit which has the additional connections required to perform adequate testing of the states of a VLSI circuit without requiring additional external connections for this purpose. This test circuit then provides electrical information, through as few external connections as possible, which is utilized in conjunction with an external test system to determine overall functionality of the VLSI circuit. This method is typically employed for circuits having greater than 10,000 transistors, and is often used in conjunction with any of the wafer probe methods described above in paragraphs (1), (3), and (4).
In summary, manufacturers who produce simple microelectronic circuits (on the order of 1-10 transistors) typically realize circuit yields greater than 90%, often employ no wafer probe and simply discard the defective circuits after all of the die have been assembled and tested in microelectronic packaging. These monolithic circuits are rarely larger than 5 mm.sup.2 in their die areas. Manufacturers who do perform wafer probe per paragraph (1) above are producing circuits which yield typically between 10% and 90%, have between approximately 10 and 100,000 transistors per circuit, and which are typically between 2 mm.sup.2 and 100 mm.sup.2 in area. Manufacturers patterning circuits greater than 100 mm.sup.2 in area and over 100,000 transistors often employ one of the methods per paragraphs (3) or (4) above where otherwise the producing yields for these circuits would be less than 10% if using either of the methods per paragraphs (1) or (2) above.
It is clear from the above summary that a relationship exists between circuit pattern size and circuit statistical yield following electrical testing. Several models that predict accurate yield statistics in a wafer fabrication environment have been developed and are understood by those skilled in the art. Each of these models identify a statistical figure of merit for the characteristic density of defects applicable to the particular wafer process technology employed. A parameter for the density of defects, established by special electrical test patterns on representative wafers, quantifies the average number of defects per unit area on the basis that each of these defects is sufficient to cause a fatal electrical failure of the circuit in which it resides.
Yield models such as Murphy & Seeds See "Semiconductor Technology Handbook", Technology Associates Inc., pp. 15-3-15-7 (1982)] or the Gamma Function [See "VLSI Technology", S. M. Sze, McGraw Hill, pp. 607-612 (1983)] have been used to describe the yield statistics for each of the prior art methodologies per paragraphs (1) through (4) above. Each of these models illustrates that increasing the pattern size of the circuit will reduce the electrical test yield, given a constant density of defects for wafer fabrication. More sophisticated models have been demonstrated which identify separate defect density parameters for separate portions of the wafer fabrication process, as well as to accurately predict the yield statistics for very large circuits.
The Murphy & Seeds models have been historically employed to predict accurate electrical test yields for circuits of various physical sizes and complexities, manufactured with various bipolar and MOS wafer fabrication technologies. As the preferred embodiment of this invention pertains to the fabrication of very large circuits based on using any of these prior art fabrication technologies, and in an effort to be representative in the demonstration of the changes in yield which are caused through the use of the present invention, the Murphy & Seeds models will be employed uniformly throughout the description of the preferred embodiment.